FIG. 1 is a block diagram showing a data communicating method performed between a main unit of a conventional apparatus (hereinafter referred to as main unit 1) and an IC card 2. To perform a data communication between the main unit 1 and the IC card 2, a clock signal and a data signal that is input and output in synchronization therewith are used. While the data signal is bi-directionally communicated between the main unit 1 and the IC card 2, the clock signal is one-directionally communicated from the main unit 1 to the IC card 2.
FIG. 2 is a block diagram showing a detailed structure of the system shown in FIG. 1. In FIG. 2, reference characters FF1R, FF1S, FF2R, and FF2S represent flip-flops. Each of the flip-flops FF1R, FF1S, FF2R, and FF2S has a data input D and a data output Q. Reference characters 101R, 102R, and CLK1 represent input buffers. Reference characters 101S, 102S, and CLK0 represent output buffers. Reference characters 101S, 102S, 101R, and 102R are composed of tri-state buffers. The main unit 1 has a clock generator 3 that generates a clock signal. Reference characters 1DE and 2DE represent control signals. Reference characters DATA and CLK represent a data transmission path and a clock transmission path disposed between the main unit 1 and the IC card 2, respectively.
First of all, the case that a data communication is performed from the main unit 1 to the IC card 2 will be described. The control signal 1DE causes the tri-state buffer 101S to be set to an output enable state. The control signal 2DE causes the tri-state buffer 102S to be set to an output high impedance state. Thus, data is transmitted from the flip-flop FF1S to the flip-flop FF2R. The clock signal is generated by the clock generator 3 of the main unit 1. The clock signal is input to the clock input of the flip-flop FF2R through a path of (output buffer CLK0->transmission path CLK->input buffer CLK1).
The data signal is output from the flip-flop FF1S in synchronization with a leading edge of the clock signal that is input from the clock generator 3 to the clock input of the flip-flop FF1S. The data signal is input to the data input of the flip-flop FF2R through a path of (output buffer 101S->transmission path DATA->input buffer 102R). The data signal is captured in synchronization with a leading edge of the clock input of the flip-flop FF2R.
Next, the case that a data communication is performed from the IC card 2 to the main unit 1 will be described. The control signal 1DE causes the tri-state buffer. 101S to be set to an output high impedance state. The control signal 2DE causes the tri-state buffer 102S to be set to an output enable state. Thus, a data transmission is performed from the flip-flop FF2S to the flip-flop FF1R. The clock signal is generated by the clock generator 3 of the main unit 1. The clock signal is input to the clock input of the flip-flop FF1R.
The data signal is output from the flip-flop FF2S in synchronization with a leading edge of the clock signal that is input to the clock input of the flip-flop FF2S through a path of (clock generator 3->output buffer CLK0->transmission path CLK->input buffer CLK1). The data signal is input to the data input of the flip-flop FF1R through a path of (output buffer 102S->transmission path DATA->input buffer 101R). The data signal is captured in synchronization with a leading edge of the clock input of the flip-flop FF1R.
FIG. 3 is a schematic diagram showing the structure of a system that performs a data communication from the IC card 2 to the main unit 1. FIG. 4 is a timing chart showing the data communication performed by the system shown in FIG. 3. Next, the system and timing chart of the data communication performed thereby shown in FIGS. 3 and 4 will be described.
As shown in FIG. 3, when the data communication is performed from the IC card 2 to the main unit 1, the data signal is transmitted from the flip-flop FF2S to the flip-flop FF1R. The clock signal that is input to the flip-flop FF2S has a delay that is the sum of a delay due to the output buffer CLK0, a delay due to the transmission path CLK, and a delay due to the input buffer CLK1 against the clock signal that is input to the flip-flop FF1R. The sum of the delays is denoted by clock delay TD1.
A delay after a leading edge of the clock input of the flip-flop FF2S until the arrival of the clock signal to the data input of the flip-flop FF1R is the sum of a delay due to the flip-flop FF2S, a delay due to the output buffer 102S, a delay due to the transmission path DATA, and a delay of the input buffer 101R. The delay due to the flip-flop FF2S is denoted by data delay TD3. The sum of the delay due to the tri-state buffer 102S, the delay due to the transmission path DATA, and the delay due to the input buffer 101R is denoted by data delay TD2.
The data that is output in synchronization with the clock input of the flip-flop FF2S should arrive at the data input of the flip-flop FF1R by the next leading edge of the clock input of the flip-flop FF1R. However, since there are clock delay TD1 and data delays TD2 and TD3, the timing tolerance becomes insufficient as shown in FIG. 4. As a result, although it is necessary to shorten the clock period for a higher data communication, a clock period equal to or lower than (delay TD1+delay TD2+delay TD3) cannot be accomplished.
Therefor, an object of the present invention is to provide an IC card and an IC card system that have a structure that allows the difference between the delay time of the clock signal and the delay time of the data signal to become zero so that a communication for data that is output from the IC card can be performed at higher speed than before and a larger amount of data can be transmitted in a shorter time than before.